PDK-driven design methods and processes are critical for silicon photonics to meet the reliability and cost targets needed for widespread commercial adoption, and accurate chip level simulation models are a critical aspect of the PDK offering.
Vancouver, BC (PRWEB)
March 15, 2017
Lumerical (http://www.lumerical.com) announced today the availability of a calibrated compact model library (CML) for imec’s 50Gb/s wafer-scale integrated silicon photonics platform (iSiPP50G) and process design kit (PDK). The Lumerical iSiPP50G CML enables circuit designers to accurately simulate and optimize photonic integrated circuit (PIC) behavior and performance prior to fabrication, reducing costly design errors and enabling first-time-right designs within Lumerical’s PIC simulator, INTERCONNECT.
Silicon photonics is emerging as a leading technology to address the challenges facing today’s rapidly evolving connected world. Driven by ever-increasing demands for high-performance optical communication systems, silicon photonics applications are expanding to include board- and chip-level interconnect, diagnostics, and other applications in health-care, environmental sensing, augmented and virtual reality and quantum computing.
The Lumerical iSiPP50G CML enables users to accurately simulate, analyze, and optimize designs using INTERCONNECT prior to fabrication and ensures design intent matches physical device operation. INTERCONNECT operates as a standalone schematic design and simulation environment, or integrates into select EDA-centric workflows for complete chip design and layout.
“By combining measured data from multiple imec wafer runs with key operating parameters extracted from our component level simulation tools, we can generate calibrated compact models for each component that chip designers…